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Analog-to-digital converter survey and analysis

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1 Author(s)
R. H. Walden ; HRL Lab. LLC, Malibu, CA, USA

Analog-to-digital converters (ADCs) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADCs, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Gs/s), resolution appears to be limited by thermal noise. At sampling rates ranging from ~2 Ms/s to ~4 giga samples per second (Gs/s), resolution falls off by ~1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADCs operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The trend toward single-chip ADCs brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only ~1.5 bits for any given sampling frequency over the last six-eight years

Published in:

IEEE Journal on Selected Areas in Communications  (Volume:17 ,  Issue: 4 )