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High-speed DRAM architecture development

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2 Author(s)
H. Ikeda ; NEC Corp., Sagamihara, Japan ; H. Inukai

This paper is an overview of the high-speed DRAM architecture developments. We discuss developments on density growth, interface technology, memory-core architecture, and DRAM+ASIC technology. We can find the developments of density as 2× growth instead of 4× by each generation. Interface technologies will have a tendency to use the terminated bus structure for higher data rate. Memory-core architecture developments are the trials for actual bandwidth improvements. DRAM+ASIC technologies seem to require universal interface solutions. We tried to show that no single solution is able to cover the wide diversity of future system requirements

Published in:

IEEE Journal of Solid-State Circuits  (Volume:34 ,  Issue: 5 )