High-speed DRAM architecture development

This paper is an overview of the high-speed DRAM architecture developments. We discuss developments on density growth, interface technology, memory-core architecture, and DRAM+ASIC technology. We can find the developments of density as 2/spl times/ growth instead of 4/spl times/ by each generation. Interface technologies will have a tendency to use the terminated bus structure for higher data rate. Memory-core architecture developments are the trials for actual bandwidth improvements. DRAM+ASIC technologies seem to require universal interface solutions. We tried to show that no single solution is able to cover the wide diversity of future system requirements.