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A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM

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4 Author(s)
Sato, T. ; Semicond. Technol. Dev. Div., Hitachi Ltd., Tokyo, Japan ; Nishio, Y. ; Sugano, T. ; Nakagome, Y.

This paper describes a 5-GByte/s data-transfer scheme suitable for synchronous DRAM memory. To achieve a higher data-transfer frequency, the properties were improved based on the frequency analysis of the memory system. Then, a bit-to-bit skew compensation technique that eliminates incongruent skew between the signals is described with a new, multioutput controlled delay circuit to accomplish bit-to-bit skew compensation by controlling transmission timing of every data bit. Simulated maximum data-transfer rate of the proposed memory system resulted in 5.1/5.8 GByte/s (321/365 MHz, ×64 bit, double data rate) for data write/read operation, respectively

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 5 )