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Accurate on-chip interconnect evaluation: a time-domain technique

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4 Author(s)
Soumyanath, K. ; Intel Corp., Hillsboro, OR, USA ; Borkar, S. ; Chunyan Zhou ; Bloechel, B.A.

This paper describes an on-chip sampling and measurement technique for accurate (<15 ps) evaluation of interconnect delays and coupled noise. We have used this nonintrusive time-domain technique to extract in situ driver/receiver waveforms, propagation delays, and coupled noise in 120 interconnect structures. The effects studied include multiple AC returns through active devices, gridded planes on adjacent layers, via impedances, variable driver impedances, and noise in bus structures. The results provide a comprehensive evaluation of interconnect delays and noise in a 1.8 V, 0.25 μm process

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Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 5 )