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A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

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2 Author(s)
A. M. Abo ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; P. R. Gray

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 μm CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW

Published in:

IEEE Journal of Solid-State Circuits  (Volume:34 ,  Issue: 5 )