14/spl mu/A Data Retention DRAM with Intermittent Bit-Line Balancing Scheme

The paper describes a 4Mb DRAM with 14muA data retention current at 3.0V. Three factors, refresh interval, back bias generation, and bit-line equalizing have been examined to cut extra power dissipation in the data retention mode. An intermittent bit-line balancing scheme is used to reduce the current from a half Vcc generator. This DRAM can also allow fast accesses (tRAC =48nsec) at 4.4V in the normal data access mode.