A High-Density Dual-Port Memory Cell Operation For ULSI DRAMs

A "truly" dual-port operation of DRAM cell is indispensable for a background refresh DRAM and pipelined high-speed DRAM cores, especially in their embedded uses. Therefore a dual-port memory array to enjoy the DRAM cell density and to suppress the array noise caused by the port interference is required in the high-density DRAM cores. A high-density 2Tr-1C dual-port DRAM cell operation in combination with a new noise-immune signal sensing scheme is proposed and demonstrated.