Design methodology for over 100MFLOPS 64bit MPU with 0.8/spl mu/m BiCMOS technology

One thousand of 100 MFLOPS processors are are needed for 0.1 TFLOPS parallel computing system as its processing elements. To previous works have shown the effectiveness of the pipeline[1] and superscalar[2] architecture for a high-speed VLSI processor, but they could not achieve over 100 MFLOPS performance. In this paper, some critical paths in superscalar architecture are analyzed and the usage of dedicated BiCMOS circuits is studied.