Referenced Items are not available for this document.
In this paper, we use the recently developed static transition diagram technique to derive analytical formulas expressing latch power in terms of true and spurious switching activities at the data input. These formulas are verified through analog simulation and applied to a number of commonly used latch designs. The derived model will allow designers to substitute parameters of true and spurious switching activities into analytical formulas for quickly obtaining accurate latch power and then select latches which have the best power-dissipation characteristics for those parameter values.
Published in:
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
(Volume:7
,
Issue:
1
)
Date of Publication: March 1999
- Page(s):
- 111 - 115
- ISSN :
- 1063-8210
- INSPEC Accession Number:
- 6200556
- Digital Object Identifier :
- 10.1109/92.748206
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- March 1999
- Sponsored by :
- IEEE Circuits and Systems Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
