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Power management in high-level synthesis

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4 Author(s)
G. Lakshminarayana ; Comput. & Commun. Res. Labs., NEC Res. Inst., Princeton, NJ, USA ; A. Raghunathan ; N. K. Jha ; S. Dey

In this paper, we present a power-management methodology targeted toward high-level synthesis of data-dominated behavioral descriptions. It is founded on the observation that variable assignment can significantly affect power-management opportunities in the synthesized architecture, i.e., variable assignment determines whether or not spurious operations get executed by functional units in the architecture. We introduce perfectly power managed architectures, whose functional units do not execute any spurious operations. We present a variable assignment technique which, when used in high-level synthesis, produces architectures which are perfectly power-managed. Unlike many previously proposed power-management techniques, our method does not add latches or any other circuitry in front of functional units or registers and is, therefore, free of the attendant performance penalty. Experimental results indicate savings of up to 52.5% (average 23.0%) in power consumption over already power-optimized architectures. The area overheads due to our technique are also low and averaged 2.5% for our examples.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:7 ,  Issue: 1 )