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Superscalar processor validation at the microarchitecture level

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3 Author(s)
N. Utamaphethai ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; R. D. Blanton ; J. P. Shen

We describe a rigorous ATPG-like methodology for validating the branch prediction mechanism of the PowerPC604 which can be easily generalized and made applicable to other processors. Test sequences based on finite state machine (FSM) testing are derived from small FSM-like models of the branch prediction mechanism. These sequences are translated into PowerPC instruction sequences. Simulation results show that 100% coverage of the targeted functionality is achieved using a very small number of simulation cycles. Simulation of some real programs against the same targeted functionality produces coverages that range between 34% and 75% with four orders of magnitude more cycles. We also use mutation analysis to modify some functionality of the behavioral model to further illustrate the effectiveness of our generated sequence. Simulation results show that all 54 mutants in the branch prediction functionality can be detected by measuring transition coverage

Published in:

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Date of Conference:

7-10 Jan 1999