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A high-performance CMOS 32-bit parallel CRC engine

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2 Author(s)
Hobson, R.F. ; Simon Fraser Univ., Burnaby, BC, Canada ; Cheung, K.L.

Design highlights for a 32-bit parallel cyclic redundancy check (CRC) generator engine are presented. In a 0.8-μm three-layer-metal CMOS process, the engine could handle about 5 Gbps data throughput. A compact layout is achieved by predecoding eight groups of four bits followed by performing a binary tree reduction on nets that are sorted by fanout. There are six gate delays plus a single-phase clock edge-triggered register

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 2 )

Date of Publication:

Feb 1999

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