A VLSI architecture for real time processing of one-bit coded SAR signals

A novel architecture for real time synthetic aperture radar signal processing is presented. Processing of SAR data requires the convolution of a sequence of echo data with a reference function. Currently quasi real time SAR signal processing is obtained by using expensive parallel computers and FFT techniques which, however, present problems if the depth of focus is small compared to the pulse length and if range dependent motion compensation is needed. The architecture presented in this paper uses time domain processing which overcomes the above mentioned problems. Real time processing is achieved by using a signum coded algorithm in which raw data and reference function are coded with a single bit. The architecture is based on a systolic array, ideally suited for implementation in custom VLSI circuits.