By Topic

Statistical methods for measurement reduction in semiconductor manufacturing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Babikian, R. ; Intel Ireland Ltd., Ireland ; Engelhard, C.

Measurement reduction in wafer fabrication represents a significant opportunity for cost reduction and improvement in operational efficiency. This translates into savings on test wafers, metrology equipment, technician time and throughput time. With ever-increasing process complexities and moves to 300 mm technology, measurement costs are increasingly becoming an area of focus to improve manufacturing efficiency. At Intel, statistical methodologies and management systems were developed to facilitate the reduction of measurements to reduce measurement costs

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI

Date of Conference:

23-25 Sep 1998