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Architecture and design of the HiPAR-DSP, a SIMD controlled signal processor with parallel data paths, VLIW and novel memory design is presented. The processor architecture is derived from an analysis of the target algorithms and specified in VHDL on register transfer level. A team of more than 20 graduate students covered the whole design process, including the synthesizable VHDL description, synthesis, routing and backannotation as the development of a complete software development environment. The 175 mm/sup 2/, 0.5 /spl mu/m 3LM CMOS design with 1.2 million transistors operates at 80 MHz and achieves a sustained performance of more than 600 million arithmetic operations.