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IMAGE: a low cost, low power video processor for high quality motion estimation in MPEG-2 encoding

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5 Author(s)
F. mombers ; Integrated Syst. Center, Fed. Inst. of Technol., Lausanne, Switzerland ; M. Gumm ; D. Stephanie ; P. Garino
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A low cost low power architecture dedicated to perform high quality motion estimation on MPEG-2 CCIR 601 sequences is presented. The chip implements a new high performance motion estimation algorithm based on a modified genetic search strategy that can be enhanced by tracking motion vectors through successive frames. When tested on several sequences at different bit rates, the algorithm delivers nearly full search quality (less than -0.1 dB for a ±75 H/V search range) while decreasing the processing power to 0.5%. The proposed MIMD processor exposes software programmability at different levels allowing the user to define his own searching strategy and combine multiple chips in Master-Salve configuration to meet the required processing power. Moreover post-processing of motion vectors, computation of dual prime vectors for low delay coding and selection of macroblock prediction mode can be programmed on this architecture. A low power strategy was also developed that mainly relies on an adaptive clocking scheme and low power caches implementation. The chip has been integrated in a 0.35 μm 5L CMOS technology on an area of 50 mm2

Published in:

IEEE Transactions on Consumer Electronics  (Volume:44 ,  Issue: 3 )