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A scaleable FIR filter using 32-bit floating-point complex arithmetic on a configurable computing machine

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2 Author(s)
A. Walters ; Annapolis Micro Syst., MD, USA ; P. Athanas

This paper presents an approach for implementing a scalable high-performance digital filter using the WILDFORCE configurable computing platform. Although not designed specifically for signal processing, configurable computing platforms offer more flexibility for algorithms than application-specific hardware, which is often needed for instances when factors such as environment or product volume dictate alterations in computing. The added flexibility enables users to construct deep pipelines to exploit properties of specific computations. In this paper, wide 32-bit floating-point arithmetic operators have been implemented which provide compatibility with hosts machines. The filter achieves 160 MFLOPs on a single WILDFORCE configurable computing platform

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998