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50 kHz pattern recognition on the large FPGA processor Enable++

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10 Author(s)
A. Kugel ; Lehrstuhl fur Inf. V, Mannheim Univ., Germany ; K. Kornmesser ; R. Lay ; J. Ludvig
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FPGA processors are very well suited for the implementation of image processing and pattern recognition tasks. This paper describes a particularly demanding application of this type and Enable++, the FPGA processor used. The system finds particle trades in high-energy physics detector images at a rate of 100 kHz. This requires to process a data stream of up to 500 MBytes/s in real time. The algorithm and the implementation on Enable++, a general purpose FPGA processor are described. Results from a software implementation are compared with the measurements from an implementation on the CCM. This implementation is 15 times faster than the software implementation on high end computers

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998