Referenced Items are not available for this document.
A 1 Mb ferroelectric random access memory (FRAM(R)) with 15.8 /spl mu/m/sup 2/ cell size and 60 ns read/write times incorporates a one transistor, one capacitor (1T1C) architecture. Data retention reliability is improved by the use of a precharged ferroelectric capacitor reference, an in-pitch ferroelectric capacitor circuit for wordline boosting, and an optimized sensing scheme. Active power is 50 mW @ 5.0 V. PZT capacitors are used with a 0.5 /spl mu/m CMP planarized CMOS process.
Published in:
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Date of Conference: 11-13 June 1998
- Page(s):
- 242 - 245
- Meeting Date :
- 11 Jun 1998-13 Jun 1998
- Print ISBN:
- 0-7803-4766-8
- INSPEC Accession Number:
- 6103581
- Conference Location :
- Honolulu, HI, USA
- Digital Object Identifier :
- 10.1109/VLSIC.1998.688101
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
