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A 1 Mb ferroelectric random access memory (FRAM(R)) with 15.8 /spl mu/m/sup 2/ cell size and 60 ns read/write times incorporates a one transistor, one capacitor (1T1C) architecture. Data retention reliability is improved by the use of a precharged ferroelectric capacitor reference, an in-pitch ferroelectric capacitor circuit for wordline boosting, and an optimized sensing scheme. Active power is 50 mW @ 5.0 V. PZT capacitors are used with a 0.5 /spl mu/m CMP planarized CMOS process.
Date of Conference: 11-13 June 1998