Skip to Main Content
We developed a new phase detector which can perform 1:2 data demultiplexing function. A newly developed pulse compensation technique enables one to output the analog phase difference for a half-frequency clock. This circuit can be used as both a phase detector for a PLL clock recovery circuit (CRC) and a root module for an asynchronous tree-type DEMUX. Using a new combined CRC-DEMUX structure, we achieved 6 Gbps 1:8 DEMUX with CRC using a 0.18 /spl mu/m CMOS in 83 mW power consumption.