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A 0.9-ns-access, 700-MHz SRAM macro using a configurable organization technique with an automatic timing adjuster

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8 Author(s)
K. Ando ; Device Dev. Center, Hitachi Ltd., Tokyo, Japan ; K. Higeta ; Y. Fujimura ; K. Mori
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The key to improving the performance of a single chip processor is to incorporate many varieties of SRAM macros with a word/bit-flexible configuration. To improve the performance even more, a configurable organization technique featuring a leaf cell design is proposed. In applying the technique, the timing design became too critical for the high-performance processor. An automatic timing adjuster is thus proposed to adjust the sense amplifier activation timing automatically in each organization. In addition, a low Vth MOS transistor is applied in order to improve access time. To overcome the increase in current leakage due to a low Vth, a back-bias control circuit is also proposed. These techniques in conjunction with a 0.25 /spl mu/m CMOS process make it possible to achieve a 0.9 ns access, 700 MHz SRAM macro.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998