Referenced Items are not available for this document.
A double data rate (DDR) SRAM bus architecture which can eliminate any speed penalty for doubling the I/O frequency and support single data rate (SDR) compatibility has been proposed. A method to guarantee data coherency for both DDR and SDR has also been described. With this architecture, we developed a 4.5 Mb DDR SRAM. Under the typical 2.5 V condition, a 600 MHz I/O frequency was achieved.
Published in:
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Date of Conference: 11-13 June 1998
- Page(s):
- 178 - 179
- Meeting Date :
- 11 Jun 1998-13 Jun 1998
- Print ISBN:
- 0-7803-4766-8
- INSPEC Accession Number:
- 6096037
- Conference Location :
- Honolulu, HI, USA
- Digital Object Identifier :
- 10.1109/VLSIC.1998.688075
- Product Type:
- Conference Publications
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