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A 2.5 V 100 MS/s 8 bit ADC using pre-linearization input buffer and level up DAC/subtractor

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7 Author(s)
M. Sugawara ; ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan ; H. Yoshida ; M. Mitsuishi ; S. Nakamura
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This paper describes a 2.5 V 100 MS/s 8 bit subranging Analog-to-Digital Converter (ADC). To achieve such low voltage operation and high-speed conversion rate at the same time, a "pre-linearization input buffer" and "level up DAC/subtractor" have been newly developed. These circuits prevent voltage drops on the internal analog signal path and make the supply voltage reduction possible. The ADC also uses a simple encoder scheme "noise immunity encoder" that is resistant to bubbling error for thermometer code.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998