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A precise on-chip voltage generator for a giga-scale DRAM with a negative word-line scheme

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7 Author(s)
H. Tanaka ; Hitachi ULSI Eng. Corp., Tokyo, Japan ; M. Aoki ; S. Kimura ; N. Sakashita
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We have designed a precise on-chip voltage generator for giga-scale DRAMs with a negative word-line scheme. It combines a charge-pump regulator and a series-pass regulator, and includes a positive/negative offset voltage generator that uses a band-gap generator with a differential amplifier. The noise on a low-voltage word-line is suppressed to below 30 mV for the word-line transient and VBB bouncing. A DC voltage error of less than 6% without trimming is also achieved.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998