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5 GByte/s data transfer scheme with bit-to-bit skew control for synchronous DRAM

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4 Author(s)
Sato, T. ; Semicond. & Integrated Circuits Div., Hitachi Ltd., Tokyo, Japan ; Nishio, Y. ; Sugano, T. ; Nakagome, Y.

With the rapid increase of MPU's operating frequency, faster data transfer is required for memory systems. When the data bus frequency exceeds 100 MHz, controlling flight time variation becomes more crucial. This paper describes a 5 GByte/s data transfer scheme (313 MHz; /spl times/64 bit, double data rate) suitable for synchronous DRAM memory systems. A new multi-output controlled delay circuit of 30 ps resolution eliminates incongruent skew between data traces, and required improvements in the electrical characteristics are illustrated.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998