Cart (Loading....) | Create Account
Close category search window
 

A 2 V 900 MHz CMOS phase-locked loop

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jieh-Tsorng Wu ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Mu-Jung Chen ; Cheng-Chung Hsu

A 2 V 60 mW 900 MHz CMOS phase-locked loop is fabricated using a 0.6 /spl mu/m CMOS technology. The negative-G/sub m/ LC-tuned oscillator employs a variable impedance converter for frequency tuning, and shows a frequency range from 808 MHz to 920 MHz. When phase-locked to an 112.5 MHz reference, the measured phase noise of the 900 MHz output is -96.5 dBc/Hz at 100 kHz offset. Chip size is 2270/spl times/2600 /spl mu/m/sup 2/.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.