By Topic

A novel powering-down scheme for low Vt CMOS circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Kumagai, K. ; ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan ; Iwaki, H. ; Yoshida, H. ; Suzuki, H.
more authors

In this paper, a novel powering-down scheme with a virtual power/ground rails clamp (VRC) circuit is proposed. It features the 98% off-leakage current reduction, without the operating speed degradation and the high Vt transistors. The VRC scheme does not need the extra circuits and the timing design for data holding in the sleep mode. This effectiveness has been confirmed by the 24-bit multiplier-accumulator, using 0.25 /spl mu/m CMOS double-layer metal technology.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998