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10-ns row cycle DRAM using temporal data storage buffer architecture

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7 Author(s)
S. Wakayama ; Fujitsu Labs. Ltd., Kawasaki, Japan ; K. Gotoh ; M. Saito ; H. Araki
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We propose a fast row-cycle DRAM-core architecture, which employs temporal data storage buffers in the sense amplifier and pipelined row-address decoding. The temporal data storage buffers eliminated the restoring time and reduced the bit-line precharge time. The pipelined row-address decoding reduced the skew in its decoding operation. We confirmed a 10 ns row-access cycle time by SPICE simulations based on a 0.24 /spl mu/m DRAM technology.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998