A new approach for parallel simulation of VLSI circuits on a transistor level

In this paper, we present a new approach for parallel simulation of very large scale integration (VLSI) circuits on a transistor level. To achieve good parallel simulation performance on workstation clusters, low communication and coarse grain parallelization is crucial. Two main tasks have to be performed to obtain this target. First, the electronic circuit must be split into subcircuits. To do this, we present an efficient partitioning technique, which yields well-balanced partitions with few interconnects. Second, for minimizing communication between the partitions, sophisticated parallelization methods have to be applied. Therefore, we present our improved domain decomposition technique for parallel analog simulation. The excellent performance of our approach is demonstrated on several industrial VLSI designs. For the first time, good speedup results for parallel analog simulation of large industrial designs are presented.