By Topic

An asynchronous 2-D discrete cosine transform chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Smith, R. ; Theseus Logic Inc., St. Paul, MN, USA ; Fant, K. ; Parker, D. ; Stephani, R.
more authors

This paper describes a fully asynchronous two-dimensional discrete cosine transform chip. The chip has a fixed block size of 8×8 pixels and uses bit-serial arithmetic. The chip was fabricated through MOSIS using a 0.8 μ double-metal CMOS process. The 49.5 mm2 core uses ~162,000 transistors. The chip operates from 0.65 V to 7.0 V, but its pixel rate at 5.0 V, 17 MHz, is significantly below the 27 MHz simulated because none of the signal's capacitances were backextracted. In order to design a completely asynchronous chip, a FIFO-based transposition memory was used, even though it used more area than RAM-based memory. The most interesting aspects of the design are presented here: the memory control structure, the pipelining structures, the use of Xilinx FPGAs and a Quickturn emulation system for emulation, and a comparison with other synchronous and asynchronous designs

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1998. Proceedings. 1998 Fourth International Symposium on

Date of Conference:

30 Mar-2 Apr 1998