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Membership test logic for delay-insensitive codes

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1 Author(s)
Piestrak, S.J. ; Inst. of Eng. Cybern., Wroclaw Univ. of Technol., Poland

Delay-insensitive (unordered) codes have been used to encode data in various asynchronous systems such as asynchronous circuits and buses. In this paper, a new general approach to designing completion-detection circuits (completion checkers) for asynchronous circuits and systems using delay-insensitive codes is presented. It is shown that a completion-detection circuit for many delay-insensitive codes can be easily and efficiently built in a systematic way by using multi-output threshold circuits. The results presented here remain in a sharp contrast with the conclusions reached by Akella et al. (1996) where similar designs-called enumeration-based decoders-were found impractical due to excessive complexity

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1998. Proceedings. 1998 Fourth International Symposium on

Date of Conference:

30 Mar-2 Apr 1998