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Low power VLSI architectures for variable-length encoding and decoding

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2 Author(s)
S. Molloy ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; R. Jain

New low power VLSI architectures are presented for variable-length encoding and decoding. Look-up table partitioning by symbol probability is shown to reduce the total power consumption; the variable-length decoder and encoder are reduced by as much as 66% and 75%, respectively. Design examples for a subband image CODEC are presented with measurements from extracted VLSI layouts.

Published in:

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on  (Volume:2 )

Date of Conference:

3-6 Aug. 1997