By Topic

An isolated-open pattern to de-embed pad parasitics [CMOSFETs]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chung-Hwan Kim ; Semicond. Div., Electron. & Telecommun. Res. Inst., Taejon, South Korea ; Kim, Cheon Soo ; Hyun Kyu Yu ; Nam, Kee Soo

To meet radio frequency (RF) performance required in large market of wireless applications, CMOS transistors having a small unit gate width are preferred. To correctly estimate RF performance, parasitics of the on-wafer pads and interconnection metal lines should be de-embedded as in the advanced bipolar transistors. However, cutoff frequencies of small-size MOSFETs de-embedded by the conventional on-wafer dummy structures result in large overestimation. A new open pattern is proposed to solve the problem. The meaning and justification of the new de-embedding pattern are discussed

Published in:

Microwave and Guided Wave Letters, IEEE  (Volume:8 ,  Issue: 2 )