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Design methodologies for system level IP

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1 Author(s)
Martin, G. ; Cadence Design Syst. Inc., San Jose, CA, USA

System-chip design which starts at the RTL-level today has hit a plateau of productivity and re-use which can be characterised as a “Silicon Ceiling”. Breaking through this plateau and moving to higher and more effective re-use of IP blocks and system-chip architectures demands a move to a new methodology: one in which the best aspects of today's RTL based methods are retained, but complemented by new levels of abstraction and the commensurate tools to allow designers to exploit the productivity inherent in these higher levels of abstraction. In addition, the need to quickly develop design derivatives, and to differentiate products based on standards, requires an increasing use of software IP. This paper describes today's situation, the requirements to move beyond it, and sketch the outlines of near-term possible and practical solutions

Published in:

Design, Automation and Test in Europe, 1998., Proceedings

Date of Conference:

23-26 Feb 1998