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Design of an optimal test pattern generator for built-in self testing of path delay faults

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3 Author(s)
Das, D.K. ; Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India ; Chaudhuri, I. ; Bhattacharya, B.B.

A novel design of a test pattern generator (TPG) for built-in self-testing (BIST) of path delay faults, is proposed. For an n-input CUT, the TPG generates a sequence of length (n.2n+1), that includes all n.2n single-input-change (SIC) test pairs, and hence optimal. The generation of such a sequence of minimum length (i.e., n.2n+1) was an open problem. A simple iterative circuit of the TPG is then constructed. This provides minimum test application time for testing path delay faults, and compares favorably with the earlier BIST designs

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998

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