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Integrated circuit design rules represent a trade-off between the probability that a given die will yield and the physical size of that die. Optimum design rules maximize the average number of good dice on a wafer. The authors present a methodology for calculating design rules that are optimum in this sense. The development involves four points: (1) any design rule can be represented physically by a key-and-target structure; (2) such key-and-target structures lend themselves to suitable mathematical analysis; (3) the average yield of a given ensemble of design rules may be estimated by computer simulation and (4) the most efficient design rules may be estimated by the methods of stochastic optimization.