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Construction of a “Grand Pareto” for line yield loss, by process loop using limited data sets

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2 Author(s)
J. Li ; AMD, Austin, TX, USA ; M. McIntyre

Identifying defect yield loss down to a single operation would provide the ultimate understanding of that operation's contribution to yield. Unfortunately, defect detection resources are seldom available in sufficient quantity to allow a yield enhancement engineer to pinpoint yield loss contributions down to a single operation. This paper will explain a methodology to build a by-operational loop defect pareto for an entire manufacturing process, which normally has only limited inspection points in-line due to scan capacity constraints. Establishing a total line pareto is essential in effectively distributing limited engineering resources to improve yields on defect limited devices. Key enables for checking and cross referencing the validity of short loop experiments will be outlined in detail throughout the paper. This paper will illustrate how, with confidence, a “Grand Pareto” for processing can be supported by the available data. In addition, a demonstration on how loss rates partitioned between “fixed” inspection points are then allocated to the intermediate operation will be shown. This methodology is required to get a total understanding of die loss contribution. Finally we will identify follow up activities that had occurred as a result of the initial “Grand Pareto”

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI

Date of Conference:

10-12 Sep 1997