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A 65-nm energy-efficient power management with frequency-based control (FBC) is proposed to achieve the near-optimum dynamic voltage scaling (DVS) in a system-on-chip system. Since DVS and dynamic frequency scaling (DFS) operations are demanded for system processor, control loop of the proposed single-inductor dual-output (SIDO) power module is merged with the frequency-controlled phase-locked loop (PLL) to constitute the operation of hybrid control loop. This means that both DVS and DFS operations can be guaranteed and are not affected by process, supply voltage, and temperature variations. The proposed power management can receive the demand of system processor by hybrid control loop and can help realize the supply voltage with different operation tasks for near-optimum DVS operation. The fabricated chip occupies a 1.12-mm2 silicon area. Experimental results show that the SIDO power module achieves a peak efficiency of 90% and the highest power reduction of 33% with the proposed near-optimum DVS operation.