Cart (Loading....) | Create Account
Close category search window
 

A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
I-Ting Lee ; Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Yun-Ta Tsai ; Shen-Iuan Liu

A leakage-current-recycling technique is presented for phase-locked loops (PLLs) in nanoscale CMOS technology. The leakage current of the PMOS capacitor in a PLL is recycled to supply the power for a voltage-controlled oscillator, a divider, and a dual-mode phase-frequency detector. This PLL is fabricated in a 65 nm CMOS technology. The measured peak-to-peak jitter and rms jitter of this PLL at 640 MHz are 52.2 ps and 9.6 ps, respectively. Its power consumption is 1.2 mW for a 1.2 V supply voltage.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 11 )

Date of Publication:

Nov. 2012

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.