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Hardware Implementation of High Throughput RC4 algorithm

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5 Author(s)
Thi Hong Tran ; Dept. of Computer Science and Electronics, Kyushu Institute of Technology, 680-4 Iizuka Fukuoka JAPAN ; Leonardo Lanante ; Yuhei Nagao ; Masayuki Kurosaki
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In this paper, we present an efficient and high throughput hardware implementation of the RC4 algorithm. The main idea of the proposed architecture is the utilization of a tri-port RAM to reduce the memory resource and to increase throughput. The proposed design requires two clock cycles for generating one byte of ciphering key and uses only a block of 256 bytes RAM. These result in 50% increment of system throughput and three times reduction of RAM resource compared to the recent architectures. The proposed implementation supports variable key length from 8 to 128 bits and achieves 80 MB/s throughput at 160 MHz operating frequency. It aims to support the WEP security in the MAC layer of 600 Mbps 4×4 MIMO wireless LAN system based on IEEE 802.11n standard.

Published in:

2012 IEEE International Symposium on Circuits and Systems

Date of Conference:

20-23 May 2012