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A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link

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5 Author(s)
Wei-Yu Tsai ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Ching-Te Chiu ; Jen-Ming Wu ; Hsu, S.S.H.
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This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis and simulation results show that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to that in the traditional pipeline topology. To verify the functions of the proposed design, two chips are implemented with the proposed 4-to-1 MUX-FF and 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the MUX-FF and the proposed serializer with MUX-FFs are almost bit-error-free (with BER <; 10-12 ), operating at up to 6 Gbits/s and 12 Gbit/s, respectively.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:59 ,  Issue: 11 )

Date of Publication:

Nov. 2012

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