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A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers

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6 Author(s)
Hershberg, B. ; Oregon State Univ., Corvallis, OR, USA ; Weaver, S. ; Sobue, K. ; Takeuchi, S.
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A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18μm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.

Published in:

VLSI Circuits (VLSIC), 2012 Symposium on

Date of Conference:

13-15 June 2012