Referenced Items are not available for this document.
This paper presents the simultaneous switching noise (SSN) measurements, modeling, and simulation of a flip-chip complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) test chip on a multilayer ceramic ball grid array (CBGA) package. Technology and design features of the chip and package test vehicles are described. Time-domain noise measurement techniques and results are presented in detail. Circuit modeling and simulation methodologies are developed and validated by strong correlation between measurement and simulation results
Published in:
Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on
(Volume:20
,
Issue:
3
)
Date of Publication: Aug 1997
- Page(s):
- 266 - 271
- ISSN :
- 1070-9894
- INSPEC Accession Number:
- 5673475
- Digital Object Identifier :
- 10.1109/96.618226
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Aug 1997
- Sponsored by :
- IEEE Components, Packaging, and Manufacturing Technology Society
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