By Topic

A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping \Delta \Sigma TDC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Dong-Woo Jee ; Dept. of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Kyungbuk, Korea ; Young-Hun Seo ; Hong-June Park ; Jae-Yoon Sim

This paper presents a low-power noise-shaping ΔΣ time-to-digital converter (TDC) and its application to a fractional-N digital PLL. With a simple structure of single-delay-stage Δ modulator followed by a charge pump based Σ modulator, a wide range of TDC input is converted to ΔΣ modulated single bit stream without loss of signal information. The ΔΣ architecture of TDC effectively improves the conversion performance of linearity and resolution while handling a large input range due to the operation of the dual-modulus divider. In addition, with a downscaling of the amount of the single delay in Δ modulator, the signal and noise transfer characteristics of TDC can be profiled to suppress the out-band noises at the input to the loop filter, resulting in easy filtering without any extra noise cancelling scheme. The DPLL is fabricated with a 0.13 μm CMOS technology. With a loop bandwidth of 1 MHz, DPLL shows an in-band phase noise of - 107 dBc/Hz at 500 kHz offset and an out-of-band phase noise of -118.5 dBc/Hz at 3 MHz offset. The TDC consumes 1 mA.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:47 ,  Issue: 4 )