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High speed S-box architecture for Advanced Encryption Standard

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3 Author(s)
Rashmi Ramesh Rachh ; Dept. of Computer Science, KLESCET, Belgaum, India ; P. V. AnandaMohan ; B. S. Anami

This paper presents a high speed architecture for composite field arithmetic based SubBytes transformation (S-box) used in Advanced Encryption Standard (AES) encryption. The proposed architecture is derived by extending the pre-computation technique suggested recently by Liu and Parhi to a recently proposed architecture of AES S-box due to Rashmi, Mohan and Anami. The proposed design of S-box is shown to have the shortest critical path with moderate gate count requirement compared to the known composite field based S-box designs described in literature. The FPGA implementation results using Xilinx XC2V6000-6 are also provided to substantiate the claimed reduction in critical path of AES S-box.

Published in:

Internet Multimedia Systems Architecture and Application (IMSAA), 2011 IEEE 5th International Conference on

Date of Conference:

12-13 Dec. 2011