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Manufacturing test for clock-domain crossing(CDC) defects is a major challenge for multi-core system-on chip(SoC) designs in the nanometer regime. Setup- and hold time violations in flip-flops situated on clock boundaries may lead to catastrophic failures, even when circuits are equipped with synchronizers at clock boundaries. In this work, we comprehensively study the effect of CDC faults, and propose a number of fault models to target such defects. In addition, we develop an automatic test-pattern selection method for CDC fault detection. This work is motivated by the fact that CDC faults cannot always be detected by conventional ATPG methods. The results of applying the proposed method to a number of IWLS'05 benchmarks demonstrate the effectiveness of our approach.