System Maintenance:
There may be intermittent impact on performance while updates are in progress. We apologize for the inconvenience.
By Topic

Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Kamath, A. ; Inst. of Microelectron., Agency for Sci., Technol. & Res., Singapore, Singapore ; Zhixian Chen ; Nansheng Shen ; Singh, N.
more authors

This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality-wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current (<; 5 pA/μm) and high ION/IOFF ratio (>; 106). Furthermore, we briefly discuss the implication of these devices in CMOS NAND logic implementation.

Published in:

Electron Device Letters, IEEE  (Volume:33 ,  Issue: 2 )