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State space optimization within the DEVS model of computation for timing efficiency

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3 Author(s)
Molter, H.G. ; Integrated Circuits & Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany ; Seffrin, A. ; Huss, S.A.

This paper presents a state optimization approach within the Discrete Event System Specification Model of Computation. The goal of state optimization is to significantly soften the timing requirements of the model when transformed to a hardware implementation. The algorithm presented relocates the behaviour of zero-timeout states into adjacent states. Thus, the resulting model has much better timing properties, which considerably increase the amount of suitable target hardware architectures. The feasibility of the approach is demonstrated by means of a complex Digital Visual Interface controller application example.

Published in:

VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on

Date of Conference:

3-5 Oct. 2011