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This work proposes an approach to generate Dynamic Compact Thermal Models dedicated to electronic components. This one is based on the result of the European project DELPHI, which can be considered as the first step of standardization concerning the generation of behavioral models dedicated to Integrated Circuit, defined as Compact Thermal Models or by its acronym CTM. More recently, the American committee JEDEC, that specified the main thermal metrics to be used for ranking package performance, summarized its definition in JESD15-4 guideline. However the methodology is limited to the steady state and to mono-chip components, this reduces its scope. A added process capable to take into account the transient thermal behavior of electronic devices was investigated. The first results show that the final deducted DCTM is able, for different power dissipation loads, to predict the transient temperature profiles of each model node, in particular the junction, with less than ±10% of error. The new reduction process based on the extended use of the genetic algorithm fitting technique turns out relevant as well as steady-state models for the realization of dynamic compact thermal models. The next objective is to assess the process reduction for the emerging multiple chips packaging.